Determining number of DRAM accesses in Intel Sandy bridge

Hi everyone,

I have an Intel(R) Xeon(r) E5 1650 Sandy bridge processor and I would like to measure the number of memory accesses by using the

performance counters. I am only able to see two events namely 1.MEM_UOP_RETIRED.ALL_LOADS and 2. MEM_UOP_RETIRED.ALL_STORES.

Apart from these, is there any other event which can provide me more accurate values? I was not able to see the event BUS_TRANS_MEM though in Section 19.4 of Volume 3 of the Intel SW Developer's Manual.

Also, won't the loads and stores be  limited to caches in case the block is available? Is it a wise move to count these two events as the total number of memory accesses?

Thanks